Prof. Andrew Tay
Singapore University of Technology and Design
Prof Andrew Tay is currently an Adjunct Professor (previously Professor) at National University of Singapore, a Senior Research Fellow at the Singapore University of Technology and Design, and a Distinguished Visiting Professor at Central South University, Changsha, China. He is also a freelance consultant and has been consulted by more than 40 companies and organisations to date. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability), thermal management of electronics and EV battery systems, solar photovoltaics and fracture mechanics. To date he has published more than 250 technical papers, 11 keynote presentations at international conferences, 11 invited lectures, 3 panel discussions, written 3 book chapters and co-edited 4 conference proceedings and two special issues of technical journals.
Failure of IC packages can occur as a result of stresses developed within plastic-ecapsulated IC packages due to moisture absorption and mismatch in the coefficient of thermal expansion (CTE) of the different constituent materials of the package. Such hygro-thermomechanical stresses can cause failures in IC packages due to excessive stress, warpage, delamination, cracking or solder joint fatigue. Hence in the design of IC packages for good reliability, one must be able to predict the hygro-thermomechanical stresses developed in a package being designed so that the adequacy of the design can be established against some failure criteria. Over the last few decades it has been well established that the fracture mechanics approach is able to predict failure in IC devices and packages due to interfacial delamination and fracture. In this tutorial, the fundamentals of fracture mechanics and its application to analyse thermomechanical failures in IC devices and packages including some case studies will be presented and discussed.
The use of low k dielectrics in high-performance chips have given rise to delamination failures due to their poorer mechanical properties compared to traditional dielectrics such as SiO2 or TEOS. For a flip chip or wafer level package, it has been found that CTE mismatch between chip and substrate can cause thermal stress to be transmitted to the various metal and dielectric layers in the chip which can induce fractures within the microcircuit resulting in structural and electrical failure. In this tutorial, some case studies will be presented which illustrate how fracture mechanics methodology can be used to identify regions of failure.
The use of silicon interposers has been introduced to overcome the problems arising from CTE mismatch between chip and substratementioned above. The development of 3D ICs and the use of TSVs is proliferating at a rapid pace. Much of the analysis of such complex 3D structures is being done using finite element simulation. While the finite element method itself has been proven to be accurate and reliable, often the assumptions made on material properties and boundary conditions are less certain. Hence some means of experimental verification will be most desirable, preferably non-destructive. This is a challenging task as TSVs and other components are embedded inside the silicon.One non-destructive technique for this is the synchrotronX-ray micro-diffraction (mXRD) technique which can be used to measure in-situstresses in TSVs and the silicon material in their vicinity. Some case studies will br presented.
Mario Lanza is a Young 1000 Talent professor at the Institute of Functional Nano & Soft Materials, at Soochow University. Dr. Lanza got his PhD with honors in 2010 at the Electronic Engineering Department of Universitat Autonoma de Barcelona. During the PhD he was a visiting scholar at The University of Manchester (UK) and he worked on different projects for Infineon Technologies. In 2010 and 2011 he completed a postdoc at Peking University, where he worked on 2D materials, and in 2012 and 2013 he was Marie Curie postdoctoral fellow at Stanford University, where he worked with Paul C. McIntyre and Hongjie Dai. Dr. Lanza has published over 55 research papers, including Science, Advanced Materials, Nanoscale, Applied Physics Letters and IEEE journals, as well as four patents and four book chapters. He is best known for his reliability studies of nanoelectronic devices, especially those using conductive AFM, a field in which he is editing an entire book for Wiley-VCH. Currently, Dr. Lanza is leading a research group formed by two postdocs, ten graduate students and two visiting scholars.
The conductive atomic force microscope (CAFM) has become one of the most useful techniques to analyze the electronic properties of many materials and electronic devices at the nanoscale. In this presentation I will show the capabilities of the CAFM to study many crucial nanoscale phenomena of thin dielectrics, such as the effect of thermal annealing, polycrystallization, thickness fluctuations, local defects, charge trapping and de-trapping, stress-induced leakage current, negative bias temperature instability and dielectric breakdown and resistive switching. I will present our last results combining electronic and mechanical CAFM stresses for studying the local properties of thin dielectrics, and I will demonstrate the direct link between resistive switching and mechanical strength, a phenomenon that could be very important in flexible devices. I will focus on HfO2, Al2O3, and SiO2, although I will also present some recent data in two dimensional dielectrics (i.e. hexagonal boron nitride). I will also present how to modify a CAFM to perform advanced experiments, like applying current compliances and collect current vs. time, among others. Finally, I will give you some indications about how to perform reliable experiments and how to avoid wrong CAFM data interpretations.
Dr. Cher Ming Tan
Chang Gung University, Taiwan
Dr. Tan received his Ph.D in Electrical Engineering from the University of Toronto in 1992. He has 10 years of working experiences in reliability in electronic industry (both Singapore and Taiwan) before joining Nanyang Technological University (NTU) as faculty member in 1996 till 2014. He joined Chang Gung University, Taiwan and set up a research Center on Reliability Sciences and Technologies in Taiwan and acts as Center Director. He is Professor in Electronic Department of Chang Gung University, Chair Professor in Ming Chi University of Technology, Taiwan. He has published more than 300 International Journal and Conference papers, and giving more than 40 invited talks in International Conferences and several tutorials in International Conferences. He holds 12 patents and 1 copyright onreliability software. He has written 4 books and 3 book chapters in the field of reliability. He is an Editor of Scientific Report, Nature Publishing Group, an Editor of IEEE TDMR and Series Editor of SpringerBrief in Reliability. He is also in the Technical committee of IEEE IRPS.
Reliability analysis of microelectronics devices and circuits can be divided into two aspects, namely reliability statistics and physics of failure. This talk is focused on the physics of failure.
To ascertain the actual mechanisms of the underlying physics of failure, formulation of physical equations and their solutions are necessary. However, due to the complex nature of the physics of failure, their solutions, especially their time evolutions can be very difficult. Fortunately, with the advanced in computation power and finite element analysis, one can obtain the solutions using finite element analysis so that our understanding of the physics of failure will be completed.
This talk presented the various works the speaker has done for the past decade till now on the use of finite element analysis to understand the physics of failure. The correctness of the finite element analysis is also verified with the corresponding physical experiments and failure phenomena.
The University of Texas, USA
Dr. Bruce is a consultant with over 20 years of experience in the semiconductor industry applying optical based fault isolation techniques. He has a BS and PhD in Physics from the University of Texas at Austin and conducted postdoctoral research at Indiana University. He worked 14 years at Advanced Micro Devices, Inc. in fab processing, reliability and failure analysis. At AMD, he has developed many optical based tools and techniques for debug of microprocessors including Soft Defect Localization (SDL) for isolating speed paths and defects in IC’s, single element Time Resolved Emission (TRE), and Resistive Interconnect Localization (RIL). Mike holds 75 patents and has published numerous papers in referred journals and conferences, including a best paper and outstanding paper at ISTFA for RIL and SDL, respectively. He is current past editor of the Electronic Device Failure Analysis magazine and has served on numerous technical committees at Sematech, ISTFA, IPFA, and IRPS.
This tutorial will cover advanced fault isolation techniques and case studies for logic debug. Fault isolation involves nondestructive analysis of a device to localize a fault or improve the performance. Specific fault isolation techniques such as Photon Emission Microscopy, Time Resolved Emission (TRE), Laser Timing Probe (LTP), Frequency Mapping (FM), Laser Assisted Device Alteration (LADA), and Soft Defect Localization (SDL) will be presented and illustrated with case studies. In addition, backgroundrequirements such as sample prep, backside solid immersion microscopy, probing and tester platforms, thermal solutions, etc, will be discussed throughout.Finally, future challenges will be discussed as devices continue to scale down below 10nm.
Kristof Croes received his BSc in physics at the Catholic University of Louvain (Belgium) in 1993 and his MSc in biostatistics at the Limburgs Universitair Centrum (LUC) in 1994. In 1999, he obtained his PhD, concerning the development of statistical techniques for planning reliability experiments. After that, he joined the reliability business unit of XPEQT, first as the software responsible and than as the manager of the R&D. From 2003 till end 2006, he was product and application manager of the package level reliability products of the Singaporean based company Chiron holdings. Beginning 2007, he went back to research, working as a BEOL reliability engineer in imec. Currently, he is group leader of the Reliability, Electrical test and Modeling group working on test, characterization (electrical, thermal and (thermo)-mechanical) and reliability with main focus on advanced interconnects (2D, 3D, OIO). Kristof was an (invited/tutorial) speaker at several leading egde semi-conductor conferences (IRPS, IITC, IEDM, ...). He also (co)-authored >100 papers in the field of reliability.
This tutorial covers the basics of the main reliability concerns in on-chip BEOL interconnects. Each concern will both be treated both from theoretical and a practical viewpoint. During the theoretical part, the basics of each mechanism will be explained and the physics behind will be introduced. During the more practical part, an engineering style will be used, where practical guidelines will be given to the reliability engineer in charge of on-chip BEOL reliability. In particular, the following reliability concerns will be dealt with:
The presentation will not be overloaded with too many details and room for questions/interactions with the audience will be foreseen if needed.
Ben Kaczer is a Principal Scientist at imec. He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively.For his Ph.D. research on the ballistic-electron emission microscopy of SiO2 and SiC films he received the OSU Presidential Fellowship and support from Texas Instruments, Inc. In 1998 he joined the front-end reliability group of imec, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge, SiGe, III-V, and MIM devices. He has co-authored more than 400 journal and conference papers and 3 patents, presented a number of invited papers and tutorials, and co-received 7 IEEE IRPS Best or Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, WoDiM, and ICICDT conferences. He is currently serving on the IEEE T. Electron Dev. Editorial Board.
As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated atomic-sized defects in the gate oxide. Literally only a handful of such defects is present in each deeply scaled device, while their behavior is typically stochastic, voltage and temperature dependent, and widely distributed in time. Consequently, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and time-dependent variability of future deeply scaled devices can be understood from the perspective of these individual defects. We will first discuss the basic physical properties of individual defects. We will then show how these properties can be described statistically, combined with actual workloads and propagated to higher design abstraction levels to project device and circuit lifetime distributions.