Keynote Speakers 


Electrostatic Discharge (ESD) Protection in Emerging Technologies: Challenges and Solutions

Prof.Juin J. Liou

Emoat, LLC, Orlando, Florida, USA

Speaker bio:

Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering at the University of Central Florida (UCF), Orlando, Florida where he is now the UCF Pegasus Distinguished Professor and Lockheed Martin St. Laurent Professor of Engineering. His current research interests are Micro/nanoelectronics computer-aided design, RF device modeling and simulation, and electrostatic discharge (ESD) protection design and simulation. Dr. Liou holds 8 U.S. patents (4 more filed and pending), and has published 10 books, more than 270 journal papers (including 18 invited review articles), and more than 220 papers (including more than 90 keynote and invited papers) in international and national conference proceedings.


Electrostatic discharge (ESD) is a process in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the object within a very short period of time [1-2]. When a microchip or electronic system is subject to an ESD event, the huge ESD-induced current can likely damage the microchip and cause malfunction to the electronic system if the heat generated in the object cannot be dissipated quickly enough. It is estimated that about 35% of all single-event catastrophic damages are ESD related, resulting in a revenue loss of several hundred million dollars in the global semiconductor industry every year [3]. The continuing diminishing in the size of MOS devices makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical component to the successful development of any next-generation electron devices, circuits, and systems.

Advancement of low-voltage electronics has been benefitted largely by the continue scaling of CMOS dimension, which is now reaching an astonishing milestone of 10-nm node. Beyond that, several new features will need to be implemented to enable the continuation of CMOS miniaturization. A noteworthy future CMOS development is the Si nanowire technology. It has the advantages of a superior gate control, excellent on-current vs. off-current ratio, very low power consumption, and extremely high cutoff frequency. The ESD protection issues of such a process are still largely unknown and need to be resolved urgently before the technology can be commercialized in the consumer market in the next few years [4]. Other non-CMOS emerging applications, including those realized in the GaN and organic technologies are increasingly important and popular in the IoT era as well. These applications impose a different set of challenges on the design and implementation of ESD protection solutions [5].    

Some comments on the ESD standards are in order. Human body model (HBM) is a mature, well-understood ESD model for simulating charge transfer from a person's finger to an electronic component. However, recent industry data indicates that the HBM rarely simulates real-world ESD failures. Latest generation package styles such as mBGAs, SOTs, SC70s, & CSPs with mm-range dimensions are often effectively too small for people to handle with fingers. Even in cases of relatively large components, most high-volume component and board manufacturing uses automated equipment, so humans rarely touch the components. Charged device model can more successfully replicate in-house and customer IC failures at the component level [6]. Nonetheless, the HBM is still frequently being used as a benchmark in the industry to evaluate the ESD effectiveness and robustness.

In the presentation, the fundamentals of ESD will first be briefly introduced. This will be followed by the exploration and evaluation of ESD protection in the emerging Si nanowire, Si FinFET, organic, and GaN technologies. Relevant challenges and solutions will be discussed.

Device variations and their effects on RRAM applications

Prof.Wei Lu

University of Michigan, Ann Arbor, MI, USA

Speaker bio:

Wei Lu is aProfessor at the Electrical Engineering and Computer Science Department at the University of Michigan – Ann Arbor, and co-founder and Chief Scientist of Crossbar Inc. He received B.S. degree in physics from Tsinghua University, Beijing, China, in 1996, and Ph.D. in physics from Rice University, Houston, TX in 2003. From 2003 to 2005, he was a postdoctoral research fellow at Harvard University, Cambridge, Massachusetts. He joined the faculty of the University of Michigan in 2005. His research interest includes high-density memory based on two-terminal resistive switches (RRAM), memristor-based neuromorphic circuits, aggressively scaled nanowire transistors, and electrical transport in low-dimensional systems. Crossbar Inc, co-founded by Prof. Lu in 2010, is a semiconductor chip company based in Silicon Valley aimed at developing and commercializing RRAM products. Crossbar Inc currently has over 60 employees and has received $85 million VC funding. To date Prof. Lu has published over 100 journal papers with over 14,000 citations. He is an associate editor for Nanoscale, and a member of the International Technology Roadmap for Semiconductors (ITRS). 


Resistive random-access memory (RRAM) has now been extensively studied for memory and computing applications. However, these devices are inherently less reliable than conventional Si devices. In this talk, the nature of RRAM device variations, include both spatial and temporal, will be discussed. Efforts on device and circuit optimizationsto mitigate or take advantage of device variations will be explored, including techniques to control the dynamic ionic migration processes and associated modeling efforts. Beyond memory, RRAM arrays have been fabricated for efficient neuromorphic computing hardware systems. The effects of device variations on feature extraction and classification will also be discussed. 


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