Invited Speakers

ESD-Induced Latchup-Like Failure in a Touch Panel Control IC

 Prof.Ming-Dou Ker

 NCTU, Taiwan

 Speaker bio:

Ming-Dou Ker received the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1993. He ever worked as the Department Manager with the VLSI Design Division, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. Since 2004, he has been a Full Professor with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. During 2008~2011, he was rotated to be Chair Professor and Vice President of I-Shou University, Kaohsiung, Taiwan. Now, he has been the Distinguished Professor in the Institute of Electronics, National Chiao-Tung University, Taiwan. He ever served as the Executive Director of National Science and Technology Program on System-on-Chipin Taiwan during 2010~2011; and the Executive Director of National Science and Technology Program on Nano Technology in Taiwan (2011~2015). During 2012~ 2015, he was the Dean of the College of Photonics, National Chiao-Tung University (NCTU), Taiwan. Currently, he is serving as the Director of the Biomedical Electronics Translational Research Center (BETRC), NCTU, working on biomedical electronics translational projects. In the technical field of reliability and quality design for microelectronic circuits and systems, he has published over 500 technical papers in international journals and conferences. He has proposed many solutions to improve the reliability and quality of integrated circuits, which have been granted with hundreds of U.S. patents. He had been invited to teach and/or to consult the reliability and quality design by hundreds of design houses and semiconductor companies in the worldwide IC industry. Prof. Ker has served as member of the Technical Program Committee and the Session Chair of numerous international conferences for many years. He ever served as the Associate Editor for the IEEE Transactions on VLSI Systems, 2006-2007. He was selected as the Distinguished Lecturer in the IEEE Circuits and Systems Society (2006–2007), and in the IEEE Electron Devices Society (2008–2015). Currently, he is the Editor of IEEE Transactions on Device and Materials Reliability.Prof. Ker has been a Fellow of the IEEE since 2008. In 2015, Prof. Ker received the Award for Outstanding Science and Technology Contribution, the Executive Yuan, Taiwan.


With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD testsof HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin.Theholding voltage of the power-rail ESD clamp circuit in the high-voltagepower pin, that waslower than its normal operating voltage,caused such a latchup-like failure. Some modified solutions to rescue thislatchup-like failureinthe touch panel control ICwill be shown in the presentation.

Failure Analysis of IC Contains FinFET

Dr.Chih Hsun Chu

Materials Analysis Technology Inc., Taiwan

Speaker bio:

Chih Hsun Chu received his BS and Ph.D degree of Materials Science and Engineering from National Tsing-Hua University in Taiwan in 1981 and 1989, respectively. Currently, he is the Chief Technical Officer of the Materials Analysis Technology Inc., Taiwan.His major topic of academic research during the graduate school study was mainly focused on the electrical properties of structural defects of silicon.Dr. Chu extended his professional interest to nano structure fabrication using focused ion beam (FIB) when doing his postdoctoral research in AT&T Bell Labs. Murray Hill, NJ, during 1990 to 1991.Dr. Chu joined the National Nano Device Laboratory, National Science Council, Taiwan, after his post doctorial research in Bell Labs. During this period, ion implantation technology, shallow junction fabrication and device fabrication were his focused.

Dr. Chu commenced his career in industry since 1995. He was firstly with Mosel-Vitelic Incorporate (MVI), the first DRAM maker in Taiwan, as the department head of Core Technology   Development, Technology Development Division. Aiming for the 0.25um technology, shallow trench isolation, thin gate dielectrics, salicide technology and multi-level metallization technology are the focus.

Now Dr. Chu is the chief technical officer of MA Tech., the first materials analysis Lab in Taiwan


IC process technology development is continuously focusing in scaling of devices and in deliveringproducts with higher speeds and power efficiencies. Theconventional transistor technology with planar CMOS transistors is no longer fulfilled the need due to the short channel effectsand leakage resulted from the reduction of gate length.

To overcome this issue, a trigate device called FinFET is introduced. The FinFET is a 3D structure and it benefits from a larger electrical area than physical foot-print because the channel width W is twice the fin height plus the fin thickness and W is larger than the fin pitch.Conventionally, the failure analysis (FA) starts with electrical failure analysis (EFA) to isolate the fault and follows by the physical failure analysis (PFA) to find the root cause. However, for the advanced technology, the size of the circuit elements is scaled. The EFA result just provides a rough location of the failure. Sometimes, further fault isolation down to the transistor is needed, which can be achieved via nanoprobing, conductive atomic force microscope (AFM) or passive voltage contrast (PVC). For the final step of PFA in the FinFET case, planar transmission microscope (PV-TEM) is conducted firstly to reveal the possible failure location and followed by the cross sectional transmission microscope (XTM)  at the same location to reveal the actual root cause. In this presentation, failure cases of ICs contain FinFET are demonstrated.

Random Telegraph Noise: Measurement, Data Analysis, and Interpretation

Dr.Francesco Maria Puglisi


 Speaker bio:

Francesco Maria Puglisi (S’12 – M’15) received the Ph.D. degree in Information and Communication Technology in 2015 from University of Modena and Reggio Emilia, Italy, where he is currently a Research Associate and Adjunct Professor. His activity focuses on the characterization, physical, and compact modeling of novel transistors and nonvolatile memories, especially RRAM, focusing on noise and variability.

Dr. Puglisi authored and co-authored more than 40 technical papers and serves in the Technical Program Committee of IEEE IRPS and IEEE IPFA conferences. He is the recipient of the Best Student Paper Award at the IEEE ICICDT 2013 Conference, 29-31 May 2013, Pavia, Italy.


In recent years, the aggressive miniaturization of electron devices brought to the fore important reliability aspects that are forecasted to be even more severe at future technological nodes. Several of such issues are originated by the presence of electrically active defects within the device structure and are only partially understood. Among major defects-related concerns, Random Telegraph Noise (RTN) is a limiting factor for circuit performance and is nowadays seen as a potential showstopper for some technologies. It consists in the abrupt and random switch of the measured current/voltage among (two or more) discrete values andis attributed to charge trapping/de-trapping into/from defects in the device. Interestingly, RTN is observed in a variety of devices, despite differences in materials, concept, and manufacturing process. From this perspective, RTN can be seen not only as a reliability concern but also as a unique fingerprint that may contribute key information about device properties. Strikingly, in some novel circuit concepts, RTN is regarded as a desirable source ofentropy for security applications. To improve the actual understanding of the processes leading to RTN it is essential to develop a standard set of “golden rules” to routinely measure, analyze, and interpret RTN. Here, we discuss suitable techniques to enable RTN analysis as a reliable and multi-purpose characterization tool. This analysis framework is exploited to study defects-related reliability issues in logic(FinFETs) and memory (RRAM) devices.

Visible Light Techniques in the FinFET Era: Challenges, Threats andOpportunities

Mr. Heiko Lohrke

Technische Universität Berlin, Germany

Speaker bio:

HeikoLohrke received his Master of Engineering in Laser- and Optotechnologies from the Ernst-Abbe-Hochschule in Jena, Thuringia,Germany in 2012. In his master thesis he designed an automatic measuring station for deep ultraviolet lithography components at Carl Zeiss Jena.Currently he is a Ph.D. student at TechnischeUniversität Berlin at the semiconductor devices group of professor Christian Boit and the security in telecommunications group of professor Jean-Pierre Seifert.His main field of research is the risk assessment of laser based attacks on secure integrated circuits using failure analysis techniques. His current research in cooperation with Qualcomm and Varioscale also includes using visible light and gallium phosphide solid immersion lenses to improve laser voltage probing resolution and enable attack risk assessment for FinFET technology devices.


This work discusses visible light laser voltage probing (VIS-LVP) and gallium phosphide solid immersion lens (GaP SIL) research for Integrated Circuit (IC) analysis at Technische Universität Berlin. An overview of the challenges in connection with the ultra-precision fabrication of GaPSILs and their application is given. The use of visible light is not only opening a path for fault isolation in small geometry devices, but it also eases access to sensitive data in security relevant IC functions. As previous work has demonstrated that VIS-LVP can be realized with moderate effort, the question is raised if attackers are able to implement visible light attack techniques with moderate or even low cost. To this end, as a first step for attack risk evaluation, a visible light Laser Scanning Microscope (LSM) with a cost of less than 100 $ is presented. The current and future capabilities of such a setup are reviewed and relevant protection concepts are discussed.

The As-grown-Generation (AG) model: A reliable model for reliability prediction under real use conditions

Dr.Jian Fu Zhang 


Speaker bio:

Jian Fu Zhang received B.Eng. degree in electrical engineering from Xi’an Jiao Tong University in 1982 and Ph.D. degree from University of Liverpool in 1987. He joined Liverpool John Moores University (LJMU) in 1992 and became a Professor in 2001. Dr Zhang is the author/coauthor of over 190 journal/conference papers, including 25 invited papers/book chapters, 45 papers in IEEE transactions and Electron Device Letters, and 17 papers at IEDM/Symposium of VLSI Technology. He is/was a member of the technical program committee of several international conferences, including IEDM.Dr Zhang's current research interests are: (i) new materials and devices for future microelectronic industry; (ii) qualification, modelling, and aging prediction; and (iii) new characterisation techniques.


The negative bias temperature instability (NBTI) is limiting the device lifetime and inducing the time dependent device-to-device variations. Its reliable prediction under long term real use operation conditions is needed for qualifying process development and optimizing circuit design. The unreliability of the prediction by early models will be demonstrated and the source of their failure will be explored. The As-grown-Generation model will be presented and its capability to predict the NBTI under real use conditions will be verified against experimental data.

Atomic-scale In-situ TEM Study on Sub-10nm Structures

Prof.Sun Litao,                                                 

Southeast University, China

Speaker bio:

Prof. Litao Sun currently serves as vice dean of School of Electronic Science and Engineering, Southeast University (SEU), the deputy director of Key Lab of MEMS of Ministry of Education, and the director of SEU-FEI Nano-pico center. He is the founding chairman of IEEE Nanotechnology Council Nanjing Chapter. He received his PhD from the Shanghai Institute of Applied Physics, Chinese Academy of Sciences in 2005. He worked as a research fellow at University of Mainz, Germany from 2005 to 2008, and a visiting professor at University of Strasbourg, France from 2009 to 2010. Since 2008, he joined SEU and honored as a Distinguished Professor. Currently, his research interests focus on: (1) Dynamic in-situ experimentation in the electron microscope (Setting up a Nanolab inside a TEM for Nanoresearch); (2) Novel properties from sub-10nm materials (nanoparticles, nanowires and related 2D nanomaterials); (3) Applications of nanomaterials in environment, renewable energy and nanoelectromechanical systems. He is the author and co-author of around 150 papers on international journals including 2 in Science, 10 in Nature and Nature series journals, etc. He holds 62 Chinese patents and 2 international patents. He has given more than 50 invited talks at international conferences. He is the Review Panel member of Graphene Flagship, European Union and Member of European Science Foundation College of Expert Reviewers. He has obtained National Science Fund for Distinguished Young Scholars of China, New Century Excellent Talents in University, Outstanding Contribution Award in Graphene Standardization, Young Leading Talent in Science and Technology Innovation, Cheung Kong Scholar Chair Professors etc.


With the development of semiconductor technology, the 10 nm feature size is approaching. It is thus quite essential to explore more precise nanofabrication and characterization method to evaluate the shape/structure stability and possible new properties of sub-10-nm material components, especially under external field such as strain, electric, or thermal fields. Here we review our recent progress in atomic resolution nanofabrication and dynamic characterization of individual nanostructures and nanodevices based on the idea of "setting up a nanolab inside a transmission electron microscope". The electron beam can be used as a tool to induce nanofabrication on the atomic scale. Additional probes from a special-designed holder provide the possibility to further manipulate and measure the electric/mechanical properties of the nanostructures in the small specimen chamber of a TEM. Recently, the optical signal also was introduced into the electron microscope to enrich the coverage of investigation inside the “multifunctional nanolab”. All phenomena from the in-situ experiments can be recorded in real time with atomic resolution.

Correlating results of CDM between test element group and product level.

Dr. Teruo Suzuki


Speaker bio:

Teruo Suzuki received the B.S. degree in Electrical Engineering in 1989 from Nagoya Institute of Technology, Aichi, Japan and received the Ph.D. in 2013 from Tsukuba University, Ibaragi, Japan. In 1989, he joined Fujitsu VLSI Ltd. He was engaged in design of CMOS ASSP from 1989 to 1995. It is an Ethernet LAN controller that he was in charge, and MB86967 is still mass-produced. He has been a member of the TPC (Technical Program Committee) of the ESD Association since 2007 and IRPS since 2015. And he is a core team member in the Industry Council on ESD target levels. He received the best paper award from the 1996, 1998 and 2004 RCJ* EOS/ESD/EMC symposium, Tokyo, Japan. He successively holds the chairman of the RCJ EOS/ESD/EMC symposium from 2010.


CDM robustness is highly dependent on packaging and IC layout unlike HBM.Therefore it is difficult to predict the CDM robustness of the product usingTest Element Group(TEG). A characteristic failure mode is shown and a method to improve the correlation between TEG and product level is introduced.

Multi-Trap Energy States in GaN HEMTs: Characterization and Modeling

Dr. Xing Zhou

NTU, Singapore

Speaker bio:

Xing Zhou’s research mainly focuses on nanoscale CMOS compact model development.  His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs.  Dr. Zhou is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002.  He is a member of the modeling and simulation sub-committee for the IEEE Electron Devices Meeting (IEDM) in 2016 and 2017.  He was a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and an editor for the IEEE Electron Device Letters in 2007–2016.  Dr. Zhou is an elected member-at-large of the IEEE EDS AdCom/BoG in 2004–2009 and 2011–2016, EDS vice-president for Regions/Chapters in 2013–2015, and EDS Distinguished Lecturer since 2000.


In this work, presence of multi-trap energy (MTE) levels in the GaN energy bandgap of AlGaN/GaN HEMT is studied based on conductance method as well as temperature-dependent current transient measurements. Using conductance method, it is observed that the MTE model shows a better fit with the measurement data as compared to the single-trap energy (STE) model. Temperature-dependent current transientanalysis under fully ON-state stress conditions has also confirmed the presence of distribution of trap energy states in the GaN energy bandgap. The DC trap model is extended to capture the effect of MTE levels. For STE level, the emission-time constant factor saturates very quickly with increasing drain voltage. However, with MTE levels, the time-constant factor continues to increase and saturates at higher drain bias, exhibiting a similar trend as observed in current transient analysis under ON-state stress measurements.The DC trap model with MTE level fit nicely with the numerical simulation data, thus, justifying the physics-based model.

Circuit-based reliability consideration in FinFET technology

Dr. Yung-Huei Lee

TSMC, Taiwan

Speaker bio:

Yung-Huei Lee is Engineering Director at TSMC. He has over 30 years of Q&R and R&D experience.  He received the B.S. degree (1979) from National Chiao-Tung University, Taiwan, and the M.S. (1982) and Ph.D. (1986) in electrical engineering from The Ohio State University, USA. Dr. Lee worked at Intel (Portland Technology Development and California Technology Manufacturing) for 23 years where he held a variety of technical management roles in the advanced device, reliability and semiconductor technology development. Since 2009, Dr. Lee has been with TSMC where he is responsible for research in reliability physics and process technology qualification for advanced technology nodes and the specialty technologies. Dr. Lee has served in the technical program committee for several international conferences, such as IEDM and IRPS. He holds 8 patents and has published over 100 technical papers in semiconductor device and process technology.  Dr. Lee is a senior member of IEEE.


The continuous scaling of device dimension and the introduction of FinFET technology has led to new reliability concerns, such as Bias Temperature Instability (BTI), Stress-Induced Leakage Current (SILC), Self-Heat Effect (SHE) and Time Dependent Junction degradation (TDJD). These reliability issues become process and design bottle neck for the advanced technology development because of their stringent process requirements and the device trade-off. In this paper, we introduced the circuit–based reliability consideration to assess the practical circuit reliability limitation that closes to the real product usage. The circuit-based reliability consideration contains low percentile reliability prediction through Monte-Carlo Simulation on transistor-based TDDB model, dynamic AC reliability environment, and power consumption leakage consideration in dealing with the junction degradation, as well as the FinFET self-heat effect impact on on-state TDDB under static DC and dynamic AC stress. Through this study, we demonstrated that a circuit-based reliability model, established form the transistor-based reliability evaluation, can be used realistically in assessing product reliability down to their use conditions. 

Multiscale Modeling of Defect-Related Phenomena in high-k Based Logic and MemoryDevices

Dr.Andrea Padovani 

MDLab s.r.l., Italy

Speaker bio:

Dr. Andrea Padovani graduated in electronic engineering at the University of Modena and Reggio Emilia, Italy and got is Ph.D. from the University of Ferrara, Italy. After holding post doc, Adjunct Professor and Assistant Professor positions at the university of Modena and Reggio Emilia, Italy, in 2013 he co-founded MDLab, an Italian company developing and marketing the commercial semiconductor device simulation software Ginestra™ where he currently works.

His research interests include the modelingof dielectric degradation and breakdown of high-k/metal gate transistorsand the modeling of nonvolatilememories (charge-trapping devices, resistive random access memory and ferroelectric memories).He authored and coauthored more than 115 technical papers published on international journals and presented at international conferences.He served as a Committee Member of the IEEE International Integrated Reliability Workshop (2012-2015) and of the IEEE International Reliability Physics Symposium (2013, 2014, 2015). He currently serves as a Committee Member of theInternational Symposium on VLSI Technology, Systems and Applications (since 2013) and of the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF (since 2015).


The number and relevance of the microscopic mechanisms involved in the reliability and operation of electronic devices has grown significantly in the last years. This happened both as a consequence of thescaling-driven adoptionof new device structures and materials with quitedifferent structural properties (e.g. high-k dielectrics) and because of the introduction of novel device conceptsthat are no longer based on classical electronic processes.Defects typically play a central role in all these mechanisms that rangefromrelatively simple charge trapping and transportprocessesto more complex electron-atom interactions involvingstructural modifications of the material system(e.g. phase transition, molecular reconfiguration, metal-insulator transition, etc.).The design and optimization of conventional and novel nano-devices requires to identify, understand and controlthese microscopic processes. This goal can be achieved by employing a multiscale modeling approachas the one we present here, which relies on a material-baseddescriptionof charge transport, chemical reactions (e.g. bond breaking, oxidation) and interactions between carriers and atomic species (ions, vacancies, dangling bonds). The proposed simulation framework is applied to study defects-related phenomena in dielectric stacks used for both logic (leakage currents, degradation, BD in MOSFETs) and memory devices (RRAM operations).

Applications and trends of material analysis in electron components failure analysis techniques


Huawei, China

Speaker bio:

Zhennian Cao is a material analysis consultant at the Component Analysis Laboratory, HUAWEI Corporation since 2015. He is now involved in material failure analysis to enhance processing and reliability of all components on HUAWEI products. He has been a professor of Chemistry and was the deputy director of analytic center at South China University of Technology for many years. After that, he worked as consultant at a famous instrument company, he also involved in judicial expertise for government. He has 30 years’ experience about analytical test research and application, including spectrum analysis, complex system and unknown matter analysis, industry products failure analysis and quality control etc.


Material analysis plays an important role in components failure analysis activities; providing technical information about new components design, manufacturing and applications. With developing innovation in electron components technology, the application and instrumentation of material analysis has also advanced to keep pace.

In this paper, we will show some case histories of components material failure analysis from the communications industry, showing the significant role material analysis techniques had in the analyses, especially in-situ techniques. We also discuss analytical methods in detail and the challenges of in-situ, micro area, trace quantity and nano-scale surface status. Finally, we will discuss future trends of in-situ material analysis techniques.

Imaging Failures in Advanced Microelectronics Devices and Measuring Stresses in 3D Integrated Circuit Chips

Prof. Andrew Tay 

Singapore University of Technology and Design, Singapore 

Speaker bio:

Prof Andrew Tay is currently an Adjunct Professor (previously Professor) at National University of Singapore, a Senior Research Fellow at the Singapore University of Technology and Design, and a Distinguished Visiting Professor at Central South University, Changsha, China. He is also a freelance consultant and has been consulted by more than 40 companies and organisations to date.  He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability), thermal management of electronics and EV battery systems, solar photovoltaics and fracture mechanics. To date he has published more than 250 technical papers, 11 keynote presentations at international conferences, 11 invited lectures, 3 panel discussions, written 3 book chapters and co-edited 4 conference proceedings and two special issues of technical journals.


Detecting sub-micron time-dependent thermal defects and identifying those that represent potential device failures is a challenge in the thermal analysis of today’s complex electronic devices. The scaling of device features results in a significant reduction in time response and an increased sensitivity to transient events. With today’s complex devices very small localized temperature ‘hot spots’ can occur due to an unintended functional anomaly in a circuit with a tight design margin or a timing perturbation resulting from a small change in capacitance or another parameter elsewhere in the circuit. As device features continue to shrink so do the challenges of detecting circuit-induced thermal defects. While gaining a full understanding of the device thermal behavior is getting more difficult, extremely high power densities is increasing the importance of having this understanding. Clearly just having average temperature rise information is not sufficient, it is necessary to have a clear understanding of temperature distributions with submicron resolution to detect local hotspots and nanosecond, and even picosecond, temporal resolution to observe time-dependent thermal events with today’s high speed devices.In this presentation a relatively new technique for thermal and failure analysis called Transient ThermoreflectanceImaging (TTI) will be described. This imaging technique enables submicron spatial resolution and when combined with temporal resolution in the nanosecond range meets the requirements necessary to fully evaluate the thermal behavior and some failures of today’s advanced complex device structures. Several case studies will be described.

In recent years, to meet the requirements of miniaturization and performance, Through Silicon Via (TSV) technology has been developed to enable 3D ICs. However, due to mismatch in coefficient of thermal expansion (CTE) of TSV materials (usually copper) and silicon, stresses are developed in the silicon surrounding the TSVs which can cause fracture in the silicon or cause changes in the electron mobility in the nearby transistors, thus determining the extent of the keep-away zonewhich affects transistor density, reliability and cost. In addition, thermal treatment schemes of TSVs also change the state of stress within the TSV and the surrounding silicon. Unfortunately, TSVs are buried inside the silicon and measuring stresses in the TSV and the surrounding silicon is very challenging. A technique available for this is light synchrotron micro-Xray diffraction (mSXRD). The use of uSXRD in measuringinsitu stresses in copper TSV and the surrounding silicon will be described in this presentation.

3D-IC FPGA Developments for High Yield and High Reliability

Mr.Cheang Whang Chang

Xilinx, American

Speaker bio:

Jonathan Chang is responsible of foundry technology development in Xilinx.Providing robust and reliable 3D-IC wafer process is one of his team’s charter.  He received degrees of MS from San Jose State University, USA.  He joined Xilinx in 1997, went through from 0.18um till now more than 10 generations of technologies, from many foundries.  Currently his emphasis is on 7nm FPGA products as well as on future technologies.


3D-IC has been recognized as one of thetechnology solutions in More than Moore.  Xilinx’s 3D-IC FPGA has beenwell adopted by the industry since the firstVirtex®-7 2000T introduced in 2011.  In particular recently, data center requires largevolume of 3D-IC for its applications.  To fulfill the high demand effectively the best way is capable to provide the high yield and reliability3D-IC product supply.  The author would like to share Xilinx’s 3D-IC development experiences by means of launching process learning vehicles, pursuing early stages reliability assessment, and optimizing the process baseline.  All the development efforts paved the foundation of robust production line.  At the end, the potential future 3D-IC technologychallenges are outlined. 

3D-Reliability challenges

Kristof Croes 

IMEC, Belgium

Speaker bio:

Kristof Croes received his BSc in physics at the Catholic University of Louvain (Belgium) in 1993 and his MSc in biostatistics at the Limburgs Universitair Centrum (LUC) in 1994. In 1999, he obtained his PhD, concerning the development of statistical techniques for planning reliability experiments. After that, he joined the reliability business unit of XPEQT, first as the software responsible and than as the manager of the R&D. From 2003 till end 2006, he was product and application manager of the package level reliability products of the Singaporean based company Chiron holdings. Beginning 2007, he went back to research, working as a BEOL reliability engineer in imec. Currently, he is group leader of the Reliability, Electrical test and Modeling group working on test, characterization (electrical, thermal and (thermo)-mechanical) and reliability with main focus on advanced interconnects (2D, 3D, OIO). Kristof was an (invited/tutorial) speaker at several leading egde semi-conductor conferences (IRPS, IITC, IEDM, ...). He also (co)-authored >100 papers in the field of reliability.


3D-TSV integration allows for better performance and smaller and cheaper systems.

In this presentation, an overview of specific reliability challenges with respect to 3D-stacked ICs processing will be given. These challenges will be grouped in 4 different domains:

  • TSV-reliability itself: stress and stability of the Cu in the TSV, stress induced in the silicon, TSV barrier/liner integrity, impact of thermal budget, etc...
  • Possible impact on FEOL and BEOL performance and reliability.
  • Backside processing: thinning induced damage to the Si, effect of released copper nail, backside passivation, etc.
  • Bonding: micro-bumps reliability, IMC growth, Cu-Cu bonding issues, bonding induced stresses and damage, etc.
TiO2/SiObilayer insulating stacks for filamentary/distributed resistive switching

Prof.Mario Lanza

Soochow University

Speaker bio:

Mario Lanza is a Young 1000 Talent professor at the Institute of Functional Nano & Soft Materials, at Soochow University. Dr. Lanza got his PhD with honors in 2010 at the Electronic Engineering Department of Universitat Autonoma de Barcelona. During the PhD he was a visiting scholar at The University of Manchester (UK) and he worked on different projects for Infineon Technologies. In 2010 and 2011 he completed a postdoc at Peking University, where he worked on 2D materials, and in 2012 and 2013 he was Marie Curie postdoctoral fellow at Stanford University, where he worked with Paul C. McIntyre and Hongjie Dai. Dr. Lanza has published over 55 research papers, including Science, Advanced Materials, Nanoscale, Applied Physics Letters and IEEE journals, as well as four patents and four book chapters. He is best known for his reliability studies of nanoelectronic devices, especially those using conductive AFM, a field in which he is editing an entire book for Wiley-VCH. Currently, Dr. Lanza is leading a research group formed by two postdocs, ten graduate students and two visiting scholars. 


In this work, we present a new strategy for enhancing the performance of resistive random   access memories (RRAM), by combining filamentary and distributed working principles. The devices consist of a matrix of Ti/TiO2/SiOX/n++ Si cells, which show unprecedented 4-states hysteretic I-V curves. The filamentary  mechanism  has  been  corroborated  by  Quantum Point  Contact  (QPC)  and   Poole-Frenkel’s  theory,  and  the distributed by conductive atomic force microscopy (CAFM). 

On the Leakage Current Issues of Ultra-thin EOT High-k Gate Dielectric Films

Prof. Hei Wong 

City University of Hong Kong, Hong Kong

Speaker bio:

Hei Wong received his Ph.D. in electrical and electronic engineering from the University of Hong Kong. Dr. Wong joined the faculty of the Department of Electronic Engineering at City University of Hong Kong in 1989 and is currently a full professor of the Department. He was a visiting professor for the 21 st Century Centre of Excellent (COE21) for Photonics-Nanodevice Integration Engineering, Tokyo Institute of Technology, Japan, and Zhejiang University, China.

Dr. Wong was the chair for the IEEE ED/SSC Hong Kong Joint Chapter during 2002-2003. He is a member of the international steering committees, technical program committees, and organizing committees for many international and local conferences. Dr. Wong has served as an Associate Editor for the Microelectronics Reliability journal since 1999, a Regional Editor for IEEE EDS Newsletter during 2003-2009, an Associate Editor for IEEE Transactions on Electron Devices since 2014. He also served as the guest editors for several journals. He has served as a Distinguished Lecturer for IEEE EDS since 2002.

Dr. Wong is author or co-author of four books and over 350 papers including over 170 journal papers, dozen journal review papers and has presented many invited talks and keynote speeches at numerous international conferences. 


The introduction of high-k gate dielectric had successfully solved the gate leakage issue and kept the state-of-the-art CPU with a reasonable low standby power. The use of thick high-k material in the advanced CMOS technology has significantly reduced the gate leakage current by avoiding the direct tunneling current is a significant issue in silicon oxide based gate dielectric with thickness less than 3 nm. However, the gate leakage is now became a major concern again when the gate dielectric is further scaled down to thesubnanometer EOT range. For high-k material with a couple nanometer thick, the leakage current is even worse because of the low band offset energies and poor film properties. This paper reviews the current conduction mechanisms in high-k metal oxides. The parameters affecting the current conduction such as dielectric constant, effective mass, band offset energies, effective thickness, and oxide trap density and surface roughness, will be critically discussed. 

The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines

 Steve S. Chung

Chair Professor, National Chiao Tung University, Taiwan

Speaker bio:

STEVE S. CHUNG received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D. thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.

Currently, he is NCTU and UMC Chair Professor at the National Chiao Tung University (NCTU).  After joining NCTU in 1987, he has been the first Department Head of EECS Honors Program (2004-2005), Dean of International Affairs Office and Executive Director of school level research center, (2007-2008). He was a Research Visiting Scholar with Stanford University in 2001, and invited to teach courses in both Stanford and University of California-Merced in 2009-2010. He has been the consultant to the two world largest IC foundries, TSMC and UMC. His recent current research areas include- nanoscale CMOS devices and technology; low voltage/power design Tunneling FET, nonvolatile memory technology and reliability; and reliability physics/interface characterization. He was the first speaker (from Taiwan) to present the paper at VLSI Technology symposium in 1995 and presented more than 26 times in IEDM and VLSI conferences.

He is an IEEE Fellow, the current IEEE EDS BoG(Board of Governor) member, IEEE Distinguished Lecturer, EDS Taipei chapter chair, Editor of J-EDS, Editor of Applied Physics-A, and with past involvement as EDS AdCom member (2004-2009), EDS Regions/Chapters chair, and Editor of EDL(2002-2008). He has served on various important conference committees, including IEDM and VLSI etc. He was awarded 3 times outstanding Research Award, distinguished PI, and distinguished NSC Research Fellow, from the National Science Council; Distinguished EE Professor and Engineering Professor of the Engineering Societies in Taiwan. He received 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.


The 3D gate with good gate controllability and lightly-doped channel also allows a better suppression of variation sources, such as random-dopant fluctuation (RDF), gate work function fluctuation (WFF), random-telegraph-noise (RTN), and random-trap-fluctuation (RTF) etc. However, scale-up of fin- height and scale-down of fin-width, i.e., high-aspect-ratio of the fin, exhibits a worse oxide roughness as well as potential line variations. On the other hand, the dc and ac leakages in FinFET have always been a myth to a majority of researchers. In this talk, we will provide a systematic approach to distinguish the differences for various geometry-dependent variation sources.

A theory will be first developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide- thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.

Development of high performance self-selective cell for 3D VRRAM architecture

Prof.Hangbing Lv

Chinese Academy of Sciences, China


The presence of new conceptual nonvolatile memories (NVMs) such as resistive switching memory (RRAM), has stimulated a variety of promising applications including programmable analog circuit, massive data storage, neuromorphic computing, etc. These new emerging applications have huge demands on high integration density and low power consumption. The 3D architecture in the forms of 3D X-point or 3D vertical RRAM (VRRAM) has been received broad attention from the research community. In such arrays, correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells. In the case of 3D X-point, individual selector is allowed to configure one-selector-one-RRAM (1S1R) structure. However, in the case of 3D VRRAM, self-selective RRAM cell with build-in nonlinearity or rectifying characteristics is essential to suppress the sneak current. In this talk, the trends of memory development will be firstly presented, followed with the 3D VRRAM architectures and the state of art of the self-selective devices. Market opportunity of 3D RRAM and outlooks will be given in final.

Time-dependent failure mechanisms of GaN power devices

Dr.Enrico Zanoni 

UNIPD, Italy


Gallium Nitride (GaN) High Electron Mobility Transistors currently offer excellent characteristics for high efficiency power conversion at voltages in excess of 600 V. Enhancement-mode devices have been developed, based either on a recessed MISHEMT structure or on p-gate technologies. In both cases, the reliability of those devices seems to be strongly related to trapping effects, deep levels generation, hot electron phenomena, inducing negative and positive threshold voltage shifts and on-resistance degradation. In particular, time dependent breakdown phenomena have been identified, affecting not only the gate and insulation dielectrics, but in some cases the GaN semiconductor itself. In this talk, failure modes and mechanisms of power GaN HEMTs will be reviewed, discussing possible physical mechanisms potentially affecting their reliability, and presenting typical experiments and extrapolation laws adopted for the evaluation of their time to failure.

Reliability study of intermetallic compound by using in-situ TEM annealing at atomic scale

Prof.Wu Xing

East China Normal University, China

Speaker bio:

Wu Xing received her Bachelor of Engineering (2007) from the Xi’an Jiaotong University (XJTU) China,and Ph.D (2012) degree in Electrical Engineering from the Nanyang Technological University (NTU) Singapore. Then she worked as post-doctor at Southeast University. She is currently a full professor in department of Electrical Engineering, East China Normal University (ECNU) China. Her research interests are in-situ TEM characterization of nanostructures and nanodevices characterization, and spintronics. She has published more than 80 SCI journal papers, and 20 domestic patents. Dr. Xing Wu is honored with professor of special appointment (Eastern Scholar) in 2016, and Shanghai rising start in 2017.


The formation mechanism of Cu-Al intermetallic compound (IMC) is critical to control the contact quality of interconnections between Al bond pads and Cu wires. The in-situ TEM is a powerful tool to analyze the nanostructure in real time [1-6]. In-situ TEM technique will be in traduced to study the phase evolution and defects formation of IMC at atomic scale. TEM images reveals that the amount of IMC increases with raising temperature and duration of time. Energy dispersive spectrometer (EDX) and high resolution TEM demonstrate that the IMC is composed of CuAl2, CuAl, and Cu9Al4

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